1. Field of the Invention
The present invention relates to the field of semiconductor device fabrication. More particularly, the present invention relates to a semiconductor device comprising a gate electrode and source/drain regions, and to a method of fabricating the same.
2. Description of the Related Art
One important element of a semiconductor device is a field effect transistor (FET). The size of these field effect transistors (FETs) is decreasing at a rapid rate as the design rule of semiconductor devices becomes increasingly smaller. In addition, reducing the power consumption and increasing the operating speed of semiconductor devices are also regarded as important aims of the manufacturing process.
One problem that has been associated with manufacturing a FET on a reduced scale is that a hot carrier is injected into a gate insulating layer of the FET. However, the introduction of a lightly-doped drain (LDD) structure in the FET has overcome such a problem. One technique for fabricating an LDD structure entails forming L-shaped spacers on the both side walls of a gate electrode, and then forming a lightly-doped source/drain region by implanting ions into the substrate using the gate electrode and the L-shaped spacers as ion implantation masks.
FIG. 1 is a sectional view of a conventional semiconductor device having an L-shaped spacer disposed on the sidewall of a gate electrode, as disclosed in U.S. Pat. No. 6,087,234 entitled “Method of forming a self-aligned silicide MOSFET with an extended ultra-shallow S/D junction” and issued to Shye-Lin Wu. As shown in FIG. 1, the conventional semiconductor device includes L-shaped spacers 13 covering the side walls of a gate electrode 12 and portions of a semiconductor substrate 10 adjacent to the gate electrode 12. In FIG. 1, reference numeral “11” designates a gate insulating layer, reference numeral “14” designates a lightly-doped source/drain region, and reference numeral “15” designates a highly-doped source/drain region.
Now, various aspects of such a semiconductor device should be taken into consideration when attempting to improve the operation speed of the semiconductor device. An important one of these aspects is the matter of parasitic capacitance that exists in many portions of the semiconductor device. Parasitic capacitance gives rise to a delay in the operation of the device and hence, limits the operation speed that can be achieved by the device. One such source of parasitic capacitance exists at the gate electrode, and will be referred to as gate fringe parasitic capacitance. FIG. 1 shows the gate fringe parasitic capacitance (Cgf) of the conventional semiconductor device, which results from the L-shaped spacers 13 being interposed between and in contact with the gate electrode 12 and the lightly-doped source/drain regions 14.